1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a process for inspecting whether a resist pattern is accurately aligned to a pattern formed beforehand.
2. Description of Related Art
Semiconductor devices are manufactured by repeating a sequence of process steps which comprises forming a film, for example, a metal film entirely on a substrate in which a pattern, for example, a pattern of a field oxide layer has been already formed, forming a photoresist film entirely on the metal film, carrying out UV exposure in which ultra-violet rays are selectively irradiated on the photoresist film through a mask, developing the photoresist film to form a photoresist pattern, inspecting an alignment of the photoresist pattern to the pattern of the field oxide layer formed beforehand, and etching selectively the metal film to form a metal electrode wiring using the photoresist pattern as a mask when the photoresist pattern is confirmed by the inspecting process to be accurately positioned, that is, accurately aligned to the pattern of the field oxide layer. On the other hand, when the alignment of the photoresist pattern is determined to be wrong by the inspecting process, that is, the alignment is out of a permissible range, the photoresist pattern is completely removed without etching the metal film to re-work from forming newly a photoresist film entirely. To inspect the alignment of the photoresist pattern to the pattern formed beforehand; the pattern of the field oxide layer, a so-called vernier pattern technology is useful, in which a plurality of first rectangular patterns, in this case, oxide patterns are formed with forming the field oxide layer pattern on a semiconductor substrate, in such a manner that the centers of the first patterns are spaced apart from each other at equal first distance in the widthwise direction thereof; a plurality of second rectangular patterns are formed of the photoresist film with forming the resist pattern for the metal wiring by the UV exposure through the mask, in such a manner that the centers of the second rectangular patterns are spaced apart from each other at equal second distances in the widthwise direction thereof, the second distance being different from the first distance by 0.1 .mu.m, for example, and that the center of the center rectangular pattern among the second rectangular patterns just coincides with the center of the center rectangular pattern among the first rectangular patterns when the resist pattern for forming the metal wiring is just aligned to the pattern of the field oxide layer; and a worker visually examines through a microscope which pair of the first and second rectangular patterns coincide each other at their center. If the coinciding first and second patterns are second ones from their center ones, the resist pattern for forming the metal wiring can be confirmed to be shifted by 0.2 .mu.m from the desired position relating to the field oxide layer. The principle of the vernier pattern technology is essentially the same as that of a vernier calipers.
The vernier pattern including the first and second rectangular patterns is formed on a periphery portion of a device section in which semiconductor elements, wirings, bonding pads, etc. are formed, or is formed outside the device section such as on a chip dividing region or a scribe region such that these rectangular patterns are arranged in a first direction (horizontal direction in the plan view) to examine the alignment state in the first direction. Further, to examine the alignment state in a second direction (vertical direction in the plan view) another vernier pattern is provided on another portion outside the device section such that these rectangular patterns are arranged in the second direction. On the other hand, to evaluate the resist pattern all over the device section correctly, particularly, in a large chip or large device section in recent tendency, the vernier pattern for inspecting in the first direction is favorably provided near a center part of the outside section in the first direction along one edge of the device section, and the vernier pattern for inspecting in the second direction is favorably provided near a center area of the outside section in the second direction along another edge of the device section. As a result, the vernier pattern for the first direction and the vernier pattern for the second direction are separated from each other at a large distance. Therefore, when the alignment inspection in the first direction is conducted by a microscope, any vernier pattern for the second direction cannot be looked in the visual field of the microscope. In consequence, the time required for the step of checking the amount of resulting misalignment is increased in the manufacturing process, thus causing lowering in the processing capacity of the production line.